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Sanhuang electronics (Hong Kong) Co., Limited

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China IS42S16400J-7TL IC DRAM 64MBIT PAR 54TSOP II ISSI, Integrated Silicon Solution
China IS42S16400J-7TL IC DRAM 64MBIT PAR 54TSOP II ISSI, Integrated Silicon Solution

  1. China IS42S16400J-7TL IC DRAM 64MBIT PAR 54TSOP II ISSI, Integrated Silicon Solution

IS42S16400J-7TL IC DRAM 64MBIT PAR 54TSOP II ISSI, Integrated Silicon Solution

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  2. Price: Based on current price
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Payment Terms T/T
Supply Ability In stock
Delivery Time 3-5 work days
Packaging Details anti-static bag & cardboard box
Memory Type Volatile
Memory Format DRAM
Technology SDRAM
Memory Size 64Mbit
Memory Organization 4M x 16
Memory Interface Parallel
Clock Frequency 143 MHz
Write Cycle Time - Word, Page -
Access Time 5.4 ns
Voltage - Supply 3V ~ 3.6V
Operating Temperature 0°C ~ 70°C (TA)
Mounting Type Surface Mount
Package / Case 54-TSOP (0.400", 10.16mm Width)
Supplier Device Package 54-TSOP II
Brand Name ISSI, Integrated Silicon Solution Inc
Model Number IS42S16400J-7TL

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  1. Product Details
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Product Specification

Payment Terms T/T Supply Ability In stock
Delivery Time 3-5 work days Packaging Details anti-static bag & cardboard box
Memory Type Volatile Memory Format DRAM
Technology SDRAM Memory Size 64Mbit
Memory Organization 4M x 16 Memory Interface Parallel
Clock Frequency 143 MHz Write Cycle Time - Word, Page -
Access Time 5.4 ns Voltage - Supply 3V ~ 3.6V
Operating Temperature 0°C ~ 70°C (TA) Mounting Type Surface Mount
Package / Case 54-TSOP (0.400", 10.16mm Width) Supplier Device Package 54-TSOP II
Brand Name ISSI, Integrated Silicon Solution Inc Model Number IS42S16400J-7TL

Product Details

Description

The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits.


The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.


The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.


A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation.


SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access.


Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.

 

Features

• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length – (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Byte controlled by LDQM and UDQM
• Package: 400-mil 54-pin TSOP II
• Lead-free package is available
• Available in Industrial Temperature
• Power Down and Deep Power Down Mode
• Partial Array Self Refresh
• Temperature Compensated Self Refresh
• Output Driver Strength Selection (Please contact Product Manager for mobile function detail)

Specifications

Attribute Attribute Value
Manufacturer ISSI
Product Category Memory ICs
Series -
Packaging Tray Alternate Packaging
Package-Case 54-TSOP (0.400", 10.16mm Width)
Operating-Temperature 0°C ~ 70°C (TA)
Interface Parallel
Voltage-Supply 3 V ~ 3.6 V
Supplier-Device-Package 54-TSOP II
Memory Capacity 64M (4M x 16)
Memory-Type SDRAM
Speed 143MHz
Format-Memory RAM

Descriptions

SDRAM Memory IC 64Mb (4M x 16) Parallel 143MHz 5.4ns 54-TSOP II
DRAM Chip SDRAM 64Mbit 4Mx16 3.3V 54-Pin TSOP-II
DRAM 64M (4Mx16) 143MHz SDR SDRAM, 3.3V

Company Details

Bronze Gleitlager

,

Bronze Sleeve Bushings

 and 

Graphite Plugged Bushings

 from Quality China Factory
  • Business Type:

    Distributor/Wholesaler,Trading Company

  • Year Established:

    2005

  • Total Annual:

    1000000-3000000

  • Employee Number:

    100~150

  • Ecer Certification:

    Verified Supplier

Our company, founded in 2005, has built long-term partnerships with numerous high-quality suppliers worldwide. We specialize in providing customers with new and original products. To ensure quality, our technicians rigorously test all products before shipment, offering customers the strongest ass... Our company, founded in 2005, has built long-term partnerships with numerous high-quality suppliers worldwide. We specialize in providing customers with new and original products. To ensure quality, our technicians rigorously test all products before shipment, offering customers the strongest ass...

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Get in touch with us

  • Reach Us
  • Sanhuang electronics (Hong Kong) Co., Limited
  • No. 2520, 25th Floor, Block A, New Asia Guoli Building, Huaqiang North Street, Shenzhen, China
  • https://www.integratedcircuit-ic.com/

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