STM8S103F3P6TR Access line 8 Kbytes Flash data EEPROM 10-bit ADC 3 timers

Product Specification

STM8S103F3P6TR Access line 8 Kbytes Flash, data EEPROM,10-bit ADC, 3 timers

Features

Core

16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline

Extended instruction set Memories

Program memory:8 Kbytes Flash;dataretention 20 years at 55 °C after 10 kcycles

Data memory: 640 bytes true data EEPROM; endurance 300 kcycles

RAM: 1 Kbytes Clock, reset and supply management

2.95 to 5.5 V operating voltage

Flexible clock control, 4 master clock sources: - Low power crystal resonator oscillator - External clock input - Internal, user-trimmable 16 MHz RC - Internal low power 128 kHz RC

Clock security system with clock monitor

Power management: - Low power modes (wait, active-halt, halt) - Switch-off peripheral clocks individually

Permanentlyactive, low consumptionpower-on and power-down reset

Interrupt management

Nested interrupt controller with 32 interrupts

Up to 27 external interrupts on 6 vectors

Timers

Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM)

8-bit basic timer with 8-bit prescaler

Auto wake-up timer

Window watchdog and independent watchdog timers

Communications interfaces

UART with clock output for synchronous operation, Smartcard, IrDA, LIN master mode

SPI interface up to 8 Mbit/s

I 2C interface up to 400 Kbit/s

Analog to digital converter (ADC)

10-bit, ±1 LSB ADC with up to 5 multiplexed channels, scan mode and analog watchdog

I/Os

Up to 28 I/Os on a 32-pin package including 21 high sink outputs

Highly robust I/O design, immuneagainst current injection

Development support - Embedded single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging

Unique ID

96-bit unique key for each device

1 Introduction

Thisdatasheet contains thedescriptionof thedevicefeatures,pinout,electrical characteristics, mechanical data and ordering information. • For completeinformationonthe STM8S microcontroller memory, registersandperipherals, please refer to the STM8S microcontroller family reference manual (RM0016). • For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051). • For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). • For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044).

2 Description

The STM8S103x access line 8-bit microcontrollers offer 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: • Reduced system cost - Integrated true data EEPROM for up to 300 k write/erase cycles - High system integration level with internal clock oscillators, watchdog and brown-out reset. • Performance and robustness - 16 MHz CPU clock frequency - Robust I/O, independent watchdogs with separate clock source - Clock security system • Full documentation and a wide choice of development tools • Advanced core and peripherals made in a state-of-the art technology

Table 1: STM8S103xx access line features

4 Product overview

Thefollowingsectionintends togiveanoverview of thebasic featuresof thedevicefunctional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016).

4.1 Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

Harvard architecture

3-stage pipeline

32-bit wide program memory bus - single cycle fetching for most instructions

X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations

8-bit accumulator

24-bit program counter - 16-Mbyte linear memory space

16-bit stack pointer - access to a 64 K-level stack

 8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

20 addressing modes

Indexed indirect addressing mode for look-up tables located anywhere in the address space

Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

80 instructions with 2-byte average instruction size  

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct memory-to-memory transfers

4.2 Single wire interface module (SWIM) and debug module (DM)

The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming.

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