Anterwell Technology Ltd.
| Payment Terms | T/T, Western Union, Paypal |
| Supply Ability | 7300pcs |
| Delivery Time | 1 day |
| Packaging Details | Please contact me for details |
| supply voltage | −0.5 to +7.0 V |
| input diode current | ±20 mA |
| output diode current | ±20 mA |
| output source or sink current | ±25 mA |
| VCC or GND current | ±50 mA |
| storage temperature | −65 to +150 °C |
| power dissipation | 500 mW |
| packages | DIP14, SO14, SSOP14 and TSSOP14, DHVQFN14 |
| Brand Name | Anterwell |
| Model Number | 74HC00D |
| Certification | new & original |
| Place of Origin | original factory |
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Product Specification
| Payment Terms | T/T, Western Union, Paypal | Supply Ability | 7300pcs |
| Delivery Time | 1 day | Packaging Details | Please contact me for details |
| supply voltage | −0.5 to +7.0 V | input diode current | ±20 mA |
| output diode current | ±20 mA | output source or sink current | ±25 mA |
| VCC or GND current | ±50 mA | storage temperature | −65 to +150 °C |
| power dissipation | 500 mW | packages | DIP14, SO14, SSOP14 and TSSOP14, DHVQFN14 |
| Brand Name | Anterwell | Model Number | 74HC00D |
| Certification | new & original | Place of Origin | original factory |
| High Light | electronic integrated circuit ，linear integrated circuits | ||
74HC00; 74HCT00
Quad 2-input NAND gate
FEATURES
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC00/74HCT00 provide the 2-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
| SYMBOL | PARAMETER | CONDITIONS | TYPICAL | UNIT | |
| 74HC00 | 74HCT00 | ||||
| tPHL/tPLH | propagation delay nA, nB to nY | CL = 15 pF; VCC = 5 V | 7 | 10 | ns |
| CI | input capacitance | 3.5 | 3.5 | pF | |
| CPD | power dissipation capacitance per gate | notes 1 and 2 | 22 | 22 | pF |
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. For 74HC00 the condition is VI = GND to VCC.
For 74HCT00 the condition is VI = GND to VCC − 1.5 V.
Fig.1 Pin configuration DIP14, SO14 and (T)SSOP14.
Fig.2 Pin configuration DHVQFN14. Fig.3 Logic diagram (one gate).
Fig.4 Function diagram. Fig.5 IEC logic symbol.
Company Details
Business Type:
Distributor/Wholesaler,Trading Company
Year Established:
2004
Total Annual:
500000-1000000
Employee Number:
20~30
Ecer Certification：
Site Member
King--- Originator of ANTERWELL, engaged in the IC electronics industry in 1998 and establish ANTERWELL in 2004. The company is located in Shenzhen Huaqiang North, the largest electronic center in Asia. Our main business is the technical development and ... King--- Originator of ANTERWELL, engaged in the IC electronics industry in 1998 and establish ANTERWELL in 2004. The company is located in Shenzhen Huaqiang North, the largest electronic center in Asia. Our main business is the technical development and ...
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